Informatics Publishing Limited

S. V. Viraktamath ¹, V. Girish , Attimarad ², Praveen M. Purohit ¹, Shweta S. Kulkarni ¹, Suhas Kulkarni ¹

Affiliations
1 ECE Department, S.D.M.C.E.T, Dharwad, Karnataka, IN
2 ECE Department, D.S. College of Engineering, Bangalore, Karnataka, IN

Abstract

Turbo coding is the most commonly used error correcting scheme in wireless systems resulting in maximum Coding gain. The MAP algorithm is a basic algorithm for turbo decoding. In this paper, authors analyze the performance of turbo MAP algorithm in terms of bit error rate (BER), considering different parameters like signal to noise ratio (SNR), generator polynomials and length of generator polynomial on Additive White Gaussian Noise (AWGN) channel. Simulation of Turbo encoder and Turbo MAP decoder is done. BER and processing time are computed for a range of SNR,considering different generator polynomials of same length and also for generator polynomials of different length, keeping the input constant. Simulation results show that BER for all the generator polynomial of same length is not same for a given SNR. Same is the case with processing time. BER for a given SNR decreases as the length of generator polynomial is increased whereas processing time increases with increase in generator polynomial length.

Keywords

Convolutional Codes, Maximum A-Posteriori (MAP), Performance, Turbo Codes.

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S. V. Viraktamath ¹, G. V. Attimarad ², Prakash R. Tonse ¹

Affiliations
1 ECE Department, S.D.M.C.E.T, Dharwad, Karnataka, IN
2 ECE Department, D.S. College of Engineering, Bangalore, Karnataka, IN

Abstract

Convolutional Coding and Decoding (CODEC) is a Forward Error Correction (FEC) technique that is particularly suited for a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). The Viterbi Algorithm (VA) has been widely applied for decoding convolutionally encoded data in digital communication systems over the last 30 years. In this proposed work, the hardware implementation of Flexible Adaptive Viterbi (FAV) Decoder is discussed. For a given code, the proposed algorithm yields nearly the same error performance as the Viterbi Algorithm while requiring a substantially smaller average number of computations. For the selected design parameters of code rate = ½ and constraint length of 3, a working frequency as high as 323.520MHz is observed on implementing FAV design on Xilinx Spartan 3e Field Programmable Gate Array (FPGA). Description of the Viterbi algorithm, design methodology of implementing it in VHDL (Very High Speed Integrated Circuits Hardware Description Language) and final implementation results using Xilinx ISE software are also given.

Keywords

Adaptive Viterbi, Convolutional, FEC, Trellis.

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S. V. Viraktamath ¹, Lubna Shaikh ², Sharana Prasad Melkundi ³, Girish V. Attimarad ⁴

Affiliations
1 Department of E & CE, SDMCET, Dharwad, Karnataka, IN
2 SMCET, Dharwad, IN
3 Sankalp Semiconductor, Hubli, IN
4 E & CE Dept., Dayanand Sagar College of Engineering, Bangalore, Karnataka, IN

Abstract

Image enhancement is basically a task of applying certain transformations to an input image such that the resultant image should be more pleasant, more detailed or less noisy. In this paper an image enhancement algorithm for compressed images using the JPEG standard is presented. The basic idea of proposed algorithm is to filter the image by manipulating the DCT coefficients according to the contrast measure defined. If the enhancement is done before compression, it will reduce the compressibility of the original image. Compressed domain enhancement approach does not affect the compressibility of the original image. This also reduces storage requirements and computational complexity.

Keywords

Compression, DCT, Image, JPEG.

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S. V. Viraktamath ¹, Girish V. Attimarad ²

Affiliations
1 Department of Electronics and Communication Engineering, S.D.M. College of Engineering and Technology, Dharwad, Karnataka, IN
2 Department of Electronics and Communication Engineering, Dayanand Sagar College of Engineering, Bangalore, Karnataka, IN

Abstract

Viterbi Decoders are employed frequently in wireless digital communication systems. Many digital communication channels are affected by distributed and burst errors. In this paper the performance analysis of Convolutional encoder and Decoder (CODEC) for the distributed errors and burst errors is done, considering different constraint lengths, generator polynomials. The hard decision with ½ rate coding technique is considered in this paper. Performance analysis in terms of error correction capability of CODEC is shown through VHDL simulation.

Keywords

Burst Errors, Decoder (VD), Distributed Errors, Scrambling Interleaver, Trellis Diagram.

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S. V. Viraktamath ¹, Shweta Kulkarni ², H. Ravi ², Girish V. Attimarad ³

Affiliations
1 Department of EC&E, SDMCET, Dharwad, Karnataka, IN
2 Department of E&CE, SDMCET, Dharwad, Karnataka, IN
3 Department of EC&E, Dayanand Sagar College of Engineering Bangalore, Karnataka, IN

Abstract

In industry there is always a requirement of frequent upgradation of industrial measurement and control systems in the industrial automated manufacturing machines. The main features of real-time measurement and control system are portability and inexpensiveness that runs on different Personal Computers (PC) used in industrial process and manufacturing. The computers provide high speed, mass memory and flexibility in programming. These features support the various functions for data analysis, computing mathematical expression, display, control and communications. This paper describes the multi-channel high speed data acquisition with 12-bit resolution hardware interfaced to the PC through any hardware internal slots or ports to measure and control the real-time analog signals such as temperature, speed, pressure, flow, position, etc using personal computer. The PCI-02 version Data Acquisition (DAQ) card is used to measure and control the real-time speed of DC motor. The closed loop Proportional Integral Derivative (PID) controller is designed using Visual Engineering Environment (VEE) pro Integrated Development Environment (IDE).

Keywords

Data Acquisition, Real-Time, Speed Measurement, Control System.

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